A semiconductor memory device normally starts an operation only when internal setting values are maintained to initial values. Therefore, an initialization (reset) operation for starting the operation of the semiconductor memory device is very important.
Semiconductor memory device having a variety of functions include a plurality of circuits of which the initial conditions should be decided, in order to perform a normal operation. The initialization (reset) operation should be performed before a memory chip is operated. In general, an auto refresh operation is repetitively performed by a counting operation during an initialization mode, thereby initializing a register, a memory cell region or the like.
The auto refresh operation refers to an operation of compensating for a loss caused by a leakage current of a circuit such as a memory cell of a semiconductor memory device, according to an auto refresh signal AREF. During the initialization mode, a normal operation of the semiconductor memory device is not performed. In order for the semiconductor memory device to perform a normal operation, a screen method is required to learn an end time point of the initialization mode.
In such a screen method, the level of an initialization signal DAI (Device Auto Initialization), which transitions at a time point where the initialization mode is ended, is detected through a DQ pad of the semiconductor memory device to screen the end time point of the initialization mode.
In addition, JEDEC (Joint Electron Device Engineering Council) defines a performance time of an initialization (reset) operation according to the specification of a semiconductor memory device. In the case of an LPDDR2 memory device, the initialization operation time thereof is limited to 10 us. Therefore, the LPDDR2 memory device should terminate the initialization operation within 10 us.
The initialization operation of the semiconductor memory device will be described with reference to FIG. 1. In the following descriptions, it is assumed that the auto refresh operation is repeated six times in the initialization mode, and the pulse width of a signal for disabling an initialization signal among internal signals may vary depending on a PVT variation.
First, the semiconductor memory device enters the initialization mode, and a power-up signal PWRUP is enabled to a logic high level after a power-up period where a power supply voltage supplied from outside approaches a target level. Then, when a reset signal RESET is inputted from outside after the power-up period, a flag signal RS_FLAG is enabled to a logic high level, and an initialization signal DAI is enabled to a logic high level.
Next, a first pulse of a preliminary refresh signal AREF_PRE is generated in response to the flag signal RS_FLAG, and a second pulse of the preliminary refresh signal AREF_PRE is generated in response to a falling edge of the auto refresh signal AREF. Furthermore, pulses after the second pulse are also generated in response of falling edges of the auto refresh signal AREF. Furthermore, a refresh initialization signal INIT_AREF and a refresh counting signal AREF_CNT having the same period as the preliminary refresh signal AREF_PRE are generated.
Then, counting signals CNT<1:3> for performing an auto refresh operation six times are counted according to the refresh counting signal AREF_CNT to set up a preset combination, and the counting initialization signal INIT_CNT is then enabled at a time point t0 to terminate the counting operation.
Here, when the counting signals CNT<1:3> correspond to the preset combination, it indicates that the counting operation is performed six times to set the counting signals CNT<1:3> to a combination of ‘L, H, H’. When the counting signals CNT<1:3> are set to ‘L, H, H’, it means that the first counting signal CNT<1> is ‘L’, the second counting signal CNT<2> is ‘H’, and the third counting signal CNT<3> is ‘H’.
The initialization signal DAI is disabled when the counting initialization signal INIT_CNT is enabled to a logic high level in a period where the preliminary refresh signal AREF_PRE is at a logic high level.
However, when the preliminary refresh signal AREF_PRE has a large pulse width as shown in a period A of FIG. 1 according to a PVT variation, a pulse of the counting initialization signal INIT_CNT may overlap the pulse of the preliminary refresh signal AREF_PRE generated in response to a fifth falling edge of the auto refresh signal AREF. In this case, a preliminary initialization signal DAI_PRE is disabled, and the initialization signal DAI is disabled at a time point t1 within the auto refresh period. Therefore, the auto refresh operation may not be performed sufficiently to a preset level in the initialization mode, and the end time point of the initialization mode may not be screened with precision.